1. Field of the Invention
The present invention relates to a drive circuit and a processing circuit, and more particularly, to a drive circuit composed of a plurality of differential AB class amplifier circuits, and a processing circuit using the drive circuit.
2. Description of the Related Art
Conventionally, a drive circuit or a processing circuit of this type is composed of a plurality of differential AB class amplifier circuits to drive a plurality of analog data lines in parallel or to amplify a plurality of analog signals in parallel in low power consumption.
A conventional drive circuit for a display unit voltage-drives capacitive load such as data lines of an LCD panel in parallel to output analog signals corresponding to display data. For this purpose, a plurality of differential AB class amplifiers with so-called Rail-To-Rail input/output function in an entire range of power supply voltage between a power supply line and a ground line are used in voltage follower connection.
For example, FIG. 1 is a block diagram showing the circuit structures of a display panel and the conventional drive circuit for the display unit. Referring to FIG. 1, the conventional drive circuit for the display unit drives a display panel 8, and is composed of a control circuit 4, a gradation power source 5, a scan line drive circuit 6 and a data line drive circuit 7.
The display panel 8 is a color liquid crystal panel of an active matrix drive type, uses thin film MOS transistors (TFT) as switching elements. A pixel is arranged in the point of each of intersections of the scan lines in a row direction and the data lines in a column direction in predetermined intervals. In each pixel, a liquid crystal capacity as a capacitive load and a TFT with a gate connected with the scan line are connected in series between the data line and a common electrode line.
A scan pulse is generated by the scan line drive circuit 7 based on a horizontal sync signal and a vertical sync signal and is applied to the scan line of each row of the display panel 8. An analog data signal is generated for every color by the data line drive circuit 7 based on digital display data and is applied to the data line of each column of the display panel 8 in a state in which a common potential Vcom is applied to a common electrode line. Thus, letters and an image are displayed on the display panel 8 in full colors.
Next, the data line drive circuit 7 will be described. This data line drive circuit 7 is composed of a D/A conversion circuit 71 and an output circuit 72. The D/A conversion circuit 71 D/A-converts the display data of each column by selecting one of the gradation voltages. An output circuit 72 carries out impedance conversion, drives the data line of each column and outputs the analog display data signal. The output circuit 72 is composed of a plurality of differential AB class amplifier circuits 1, in which Rail-To-Rail input/output is possible and which are in voltage follower connection, and a common bias circuit 2 which supplies a common bias voltage to the plurality of differential AB class amplifier circuits 1. The output circuit 72 of the conventional data line drive circuit 7 uses the differential AB class amplifier circuits 1 with less power consumption are used, and the plurality of data lines can be driven in parallel while the increase of circuit scale is restrained due to the plurality of arrays of the differential AB class amplifier circuits 1, through a combination of the common bias circuit 2 and them. Thus, a circuit area is reduced and the low power consumption is realized.
FIG. 2 is a diagram showing a first conventional example of the differential AB class amplifier circuit 1, which is disclosed in Japanese Laid Open Patent Application (JP-A-Showa 61-35004). This differential AB class amplifier circuit 1 is composed of a differential amplifier 17 and an AB class output circuit 18. As a driver of the AB class output circuit, a general differential amplifier 17 in which the Rail-To-Rail input/output is possible is used. The differential amplifier 17 is composed of an N-channel differential amplifier mirror output section 171 and a P-channel differential amplifier section 172.
The differential amplifier mirror output section 171 is composed of a pair of N-channel differential MOS transistors 112 and 113, a pair of P-channel load MOS transistors 114 and 115, a pair of P-channel mirror output MOS transistors 117 and 118, and a constant current source 116. The gates of the N-channel differential MOS transistors 112 and 113 are connected with a non-inversion input terminal Vin(+) and an inversion input terminal Vin(−). The P-channel load MOS transistors 114 and 115 are connected as loads of the N-channel differential MOS transistors 112 and 113. The P-channel mirror output MOS transistors 117 and 118 output mirror currents I4 and I5 of the differential currents of the P-channel load MOS transistors 114 and 115 to the N-channel load MOS transistors 124 and 125 of the differential amplifier section 172. The constant current source 116 supplies constant current I1 to sources of the N-channel differential MOS transistors 112 and 113.
Also, the differential amplifier section 172 is composed of a pair of P-channel differential MOS transistors 122 and 123, a pair of N-channel load MOS transistors 124 and 125, a constant current source 126. The gates of the P-channel differential MOS transistors 122 and 123 are connected with the inversion input terminal Vin(−) and the non-inversion input terminal Vin(+). The N-channel load MOS transistors 124 and 125 are connected as a current mirror-type load of the P-channel differential MOS transistors 122 and 123. The constant current source 126 supplies constant current 12 to sources of the P-channel differential MOS transistors 122 and 123. A signal is outputted from the drain of the P-channel differential MOS transistor 123 to the gate of the N-channel output stage MOS transistor 132 of the AB class output circuit 18.
The AB class output circuit 18 is composed of a pair of N-channel and P-channel output stage MOS transistors 131 and 132, a pair of constant current sources 137 and 138, a pair of N-channel and P-channel shift MOS transistors 135 and 136, and a pair of constant voltage sources 139 and 140. The P-channel and N-channel output stage MOS transistors 131 and 132 are respectively connected between the output terminal and the power supply terminal and between the output terminal and the ground terminal. The constant current sources 137 and 138 are respectively connected between the gate of the P-channel output stage MOS transistors 131 and the power supply terminal and between the gate of the N-channel output stage MOS transistors 132 and the ground terminal. The P-channel and N-channel shift MOS transistors 135 and 136 function as a level shifter and are connected in parallel between the constant current sources 137 and 138. The constant voltage sources 139 and 140 supply voltages which are lower than the power supply terminal and the ground terminal by the threshold voltages of two of diode-connection P-channel and N-channel MOS transistors connected in series.
It should be noted that when the bias sections of the plurality of differential AB class amplifier circuits 1 of this conventional example should be made common, the constant current sources 116, 126, 137 and 138 of the differential AB class amplifier circuits are constituted as current mirror circuit structures. The constant current MOS transistor for the mirror output and a mirror input MOS transistor are separated. The common bias circuit 2 is composed of a mirror input MOS transistor and constant voltage sources 139 and 140. The mirror input MOS transistor supplies the bias voltage to the gate of the constant current MOS transistor of the differential AB class amplifier circuit 1.
In this conventional differential AB class amplifier circuit, two constant current sources 116 and 126 of the differential amplifier 17 are generally constituted by current mirror circuits of the N-channel and P-channel MOS transistors, respectively. The input voltage range in which the P-channel MOS transistor of the constant current source 126 can operate normally is equal to or larger than VSS, and equal to or smaller than VDD−[Vgs+Vds(sat)]. In the input voltage range larger than VDD−[Vgs+Vds(sat)], the current mirror circuit of the N-channel MOS transistor of the constant current source 116 operates normally. By the two sets of P-channel MOS transistors 114 and 117, and 115 and 118 of the current mirror circuits, the mirror currents 14 and 15 of the differential currents based on bias current I1 are folded and are supplied to N-channel load MOS transistor 124 and 125. Therefore, a differential amplifier section operates in the input voltage range from the ground terminal to the power supply terminal, and the Rail-to-rail input becomes possible. Thus, the Rail-to-rail input/output function of the differential AB class amplifier circuit is achieved.
FIG. 3 is a circuit diagram showing a second conventional example of the above-mentioned differential AB class amplifier circuit, which is disclosed in Japanese Laid Open Patent Application (JP-P2001-177352A). This conventional differential AB class amplifier circuit 1 is composed of an N-channel differential amplifier 11, a P-channel differential amplifier 12 and an AB class output circuit 13, and the Rail-To-Rail input/output function is achieved.
The differential amplifier 11 is composed of a pair of N-channel differential MOS transistors 112 and 113, a pair of P-channel load MOS transistors 114 and 115 of a current mirror type, and an N-channel constant current source MOS transistor 111. The gates of the N-channel differential MOS transistors 112 and 113 are connected with an inversion input terminal Vin(−) and a non-inversion input terminal Vin(+). The P-channel load MOS transistors 114 and 115 are connected with the N-channel differential MOS transistors 112 and 113, respectively. The N-channel constant current source MOS transistor 111 inputs bias voltage BN to its gate and supplies a source constant current I1 to the N-channel differential MOS transistors 112 and 113. The output is connected from the drain of the N-channel differential MOS transistor 113 to the gate of the P-channel output stage MOS transistor 131 of the AB class output circuit.
The differential amplifier 12 is composed of a pair of P-channel differential MOS transistors 122 and 123, a pair of N-channel load MOS transistors 124 and 125 of a current mirror type, and a P-channel constant current source MOS transistor 121. The gates of the P-channel differential MOS transistors 122 and 123 are connected with the inversion input terminal Vin(−) and the non-inversion input terminal Vin(+). The N-channel load MOS transistors 124 and 125 are connected with the P-channel differential MOS transistors 122 and 123, respectively. The P-channel constant current source MOS transistor 121 inputs the bias voltage BP to its gate and supplies a source constant current I2 to the P-channel differential MOS transistors 122 and 123. The output is connected from the drain of the P-channel differential MOS transistor 123 to the gate of the N-channel output stage MOS transistor 132 of the AB class output circuit.
The AB class output circuit 13 is composed of a pair of P-channel and N-channel output stage MOS transistors 131 and 132, a pair of P-channel and N-channel constant current MOS transistors 133 and 134, and a pair of P-channel and N-channel shift MOS transistors 135 and 136. The P-channel and N-channel output stage MOS transistors 131 and 132 are connected between the output terminal and the power supply terminal and between the output terminal and the ground terminal. The gates of the MOS transistors 131 and 132 are connected with the output lines of the differential amplifiers 11 and 12, respectively. The P-channel and N-channel constant current MOS transistors 133 and 134 are connected between the output line of the differential amplifier 11 and the power supply terminal and between the output line of the differential amplifier 12 and the ground terminal, respectively. The gates of the MOS transistors 133 and 134 are connected with the P-channel and N-channel constant current bias voltages BP and BN. The P-channel and N-channel shift MOS transistors 135 and 136 are connected between the output lines of the differential amplifiers 11 and 12 in parallel to function as level shifters. Also, the AB class output circuit 13 is composed of a pair of P-channel and N-channel mirror output MOS transistors 141 and 142, and a pair of P-channel and N-channel mirror output MOS transistors 143 and 144. The P-channel and N-channel mirror output MOS transistors 141 and 142 are connected between the gate of the N-channel shift MOS transistor 136 and the power supply terminal and between the gate of the P-channel shift MOS transistor 135 and the ground terminal. The gates of the MOS transistors 141 and 142 are connected with the bias voltages BP and BN, respectively. The P-channel and N-channel mirror output MOS transistors 143 and 144 are connected between the gate of the P-channel shift MOS transistor 135 and the power supply terminal and between the gate of the N-channel shift MOS transistor 136 and the ground terminal. The P-channel and N-channel mirror output MOS transistors 143 and 144 pass P-channel and N-channel mirror currents I7 and I6 to the output stage MOS transistors 131 and 132. Moreover, in the AB class output circuit of this conventional example, a pair of mirror capacities 145 and 146 for phase compensation are connected between the respective gates of the P-channel and N-channel output stage MOS transistors 131 and 132 and the output terminal Vout. The differential AB class amplifier circuit has a good frequency response. It should be noted that the common bias circuit 2 is composed of P-channel and N-channel mirror input MOS transistors in the current mirror circuit to supply the bias voltages BP and BN to the plurality of differential AB class amplifier circuits of this conventional example.
In this conventional differential AB class amplifier circuit 1, the bias voltages BN and BP are applied to the gates of the N-channel and P-channel mirror output MOS transistors 142 and 141 for current mirror control. Also, the P-channel and N-channel mirror output MOS transistors 143 and 144 are controlled as a current mirror, similar to the P-channel and N-channel output stage MOS transistors 131 and 132. The nodes between the MOS transistors 143 and 142 and 141 and 144 are connected with the gates of the P-channel and N-channel shift MOS transistors 135 and 136. Therefore, the gate voltages of the P-channel and N-channel shift MOS transistors 135 and 136 are not constant, unlike the first conventional example. The gate voltages thereof dynamically change in accordance with the output state of the differential AB class amplifier circuit 1 to set only one of the P-channel and N-channel output stage MOS transistors 131 and 132 to a current mirror operating state. Thus, an idling current is suppressed to a small value so that crossover distortion is reduced.
Also, in the plurality of differential AB class amplifier circuits and the common bias circuit shown in FIGS. 2 and 3, the MOS transistors of the constant current source or the constant current MOS transistors and the shift MOS transistors are controlled to be turned off in a test mode, although being not shown. Also, the P-channel and N-channel test MOS transistors are connected between the power supply terminal and the gate of the P-channel output stage MOS transistor of the AB class output circuit 13 and between the ground terminal and the gate of the N-channel output stage MOS transistor such that they are turned on in the test mode. In the test mode, the pair of P-channel and N-channel output stage MOS transistors are turned off to set the idling current to zero. Thus, in the test mode, all the circuit current paths are turned off so that a chip leak current of the data line drive circuit can be measured.
However, there are some problems in the differential AB class amplifier circuit of the conventional drive circuits.
In the differential AB class amplifier circuit of the first conventional example shown in FIG. 2, although the Rail-to-rail input/output is possible, it is necessary to fold the mirror currents I4 and I5 of the differential current based on the bias current I1 in the input voltage range of VDD−[Vgs+Vds(sat)]. For this reason, the number of elements increases for the folding mirror circuit and the consumption current increases by the mirror current I4 and I5. This hinders high integration and realization of low power consumption.
In the differential AB class amplifier circuit of the second conventional example shown in FIG. 3, when the plurality of differential AB class amplifier circuits are used as the output circuits of the data line drive circuit, the gate voltages of the P-channel and N-channel shift MOS transistors 135 and 136 change in accordance with the output state of the differential AB class amplifier circuit 1. Therefore, the gates of the P-channel and N-channel MOS transistors 135 and 136 of the plurality of differential AB class amplifier circuits 1 cannot be connected in common. For this reason, four mirror output MOS transistors 141 to 144 are needed for every differential AB class amplifier circuit. This hinders high integration.
Also, the idling currents of the output stage MOS transistors of the differential AB class amplifier circuit are controlled by the current mirror. Therefore, the consumption current increases by the current mirror currents 16 and 17 of the four mirror output MOS transistors 141 to 144 shown in FIG. 3.
Also, when these differential AB class amplifier circuits 1 are used as the output circuits 72 of the data line drive circuit 7, the P-channel and N-channel test MOS transistors are added between the gate of the P-channel output stage MOS transistor and the power supply terminal and between the gate of the P-channel output stage MOS transistor and the ground terminal, in order to turn off all the circuit current paths in the test mode. Also, the gate voltages of the P-channel and N-channel output stage MOS transistors are fixed to the bias voltages. In the drive circuit of the display unit, 300 to 500 differential AB class amplifier circuits 1 are used per chip, so that 600 to 1000 P-channel or N-channel test MOS transistors are required. This hinders high integration.
In conjunction with the above description, an MOSFET power amplifier is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 7-142940). In this conventional example, a power output stage of the MOSFET power amplifier of a push-pull type has a CMOS structure. An offset stage is provided in front of the power output stage, and an amplifier stage provided in front of the offset stage to amplify an input signal. A gate bias voltage of a MOSFET of the power output stage is set by the offset stage.
Also, an operational amplifier circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 9-232883). In this conventional example, the operational amplifier circuit is provided with first and second differential amplifier circuits with a set of first input terminal and a second input terminal, first and second level shift circuits, first and second current sources, a first and second output circuit composed of transistors. The first input terminal of the first differential amplifier circuit and the first input terminal of the second differential amplifier circuit are connected, and the second input terminal of the first differential amplifier circuit and the second input terminal of the second differential amplifier circuit are connected. The output of the first differential amplifier circuit is connected with the input of the said first level shift circuit. The output of the said first level shift circuit is connected with the first current source and the gate of a first transistor of the output circuit. The output of the second differential amplifier circuit is connected with the input of the second level shift circuit, and the output of the second level shift circuit is connected with the current source and the gate of a second transistor of the second output circuit.